Designers of integrated circuit devices (“chips”), generally application-specific integrated circuits (“ASICs”), use prototyping as part of the electronic design automation process prior to manufacture of the chip. Prototyping is one type of hardware-based functional verification that allows the circuit designer to observe the behavior of the circuit design under conditions approximating its final, manufactured performance. During prototyping, a circuit design, generally written in register transfer language (“RTL”) code, is programmed into one or more programmable logic chips, frequently field-programmable gate arrays (“FPGA”) on a prototyping hoard. FPGA-based prototypes are a fully functional representation of the circuit design, its circuit board, and its input/output (“I/O”) devices. Also, FPGA prototypes generally run at speeds much closer to the clock speed at which the manufactured chip will run than other types of functional verification, e.g., software simulation, thereby allowing for verifying the circuit design under many more conditions in the same amount of time than other verification methods, and in particular, software simulation. The circuit design prototype may also be operated in another electronic circuit, e.g., the electronic circuit for which the design under verification will be used after fabrication, so that the circuit design prototype may be observed and tested in an environment in which the manufactured chip will be used. As such, circuit designers may use FPGA prototyping as a vehicle for software co-development and validation, increasing the speed and accuracy of system developments.
Prototyping of a circuit design using programmable logic chips (e.g., FPGAs) can have advantages over other types of functional verification, namely emulation using a plurality of emulation processors. First, prototyping using programmable logic chips generally results in higher speed relative to emulation using emulation processors. Second, such higher-speed circuit design prototypes using programmable logic chips can sometimes even run in real-time, that is, the prototype may run at the intended clock speed of the manufactured chip, rather than a reduced clock speed. This is not always the case, notably for higher performance circuit designs that have clock speeds higher than the maximum allowed by the programmable logic chips. Third, such prototyping systems using programmable logic chips are generally of lower cost than an emulation system using processors.
Recently, RTL designs used for prototyping have become very large and generally need to be mapped/partitioned to several large FPGAs on a prototyping system. Typically, these large designs employ many clocks (e.g., one to one hundred or more clocks) for the operation of the design. With multiple FPGAs, interconnects are required between the FPGAs for signal flow from one portion of the circuit design logic on a first FPGA to another portion of the circuit design logic on a second FPGA and so forth. However, current FPGA designs have a limited number of interconnects, which results in overall limited bandwidth for multiple FPGA prototyping systems. In conventional designs, when design clocks are distributed over the interconnects, the system bandwidth is severely reduced for distributing other signals, leading to overall system performance degradation. One additional issue is that distributing clock signals on interconnects results in misalignment of clock edges in the different FPGAs of the system, leading to distortion in waveform capture.
Current FPGA-based prototyping systems deal with some of the problems of a limited number of FPGA I/O pins. For example, FIG. 1 illustrates a conventional prototyping design 100 having multiple FPGAs in which the clock signals are transmitted from a first FPGA 110 to a second FPGA 120. As shown, reference clock/control signals 102 can be generated by a central clock generator that is on the prototyping board, but that is not part of any FPGA hosting a circuit design partition. These signals 102 are transmitted to a clock generator 112 on first FPGA 110, which uses the reference clock as an input to further generate a set of user clocks of different frequencies required by the prototyping design. The user clocks are then provided to the logic partial design 114 on the FPGA 110 and to the logical partial design 124 of the second FPGA 120. It should be appreciated that the logic partial design of each FPGA corresponds to the actual logic of the RTL design.
Although FIG. 1 is a simplistic design of an existing FPGA prototyping system, it should be appreciated than one thousand or more signals can be transmitted between FPGA 110 and FPGA 120. One partial solution for dealing with the system's limited bandwidth is to multiplex signal pins, so that more than one signal may be carried on a single interconnect between I/O pins, freeing up I/O pins for clock signals. However, this technique is still inadequate as the number of FPGA and ASIC logic gates continue to grow in size faster than the number of available I/O pins. Moreover, the delays incurred on the clocks themselves will cause clock misalignment among the chips, requiring the gates they feed to slow down in order to compensate for the delays. This problem is amplified when more FPGAs are included in the prototyping system, as each destination FPGA will likely have a different delay value.